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syncmos technologies international, inc. sm89s16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & rtc & adc & pwm & pdwu embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm89s16r1 08/2006 1 product list SM89S16R1L25, 25mhz 64kb internal flash mcu sm89s16r1c25, 25mhz 64kb internal flash mcu sm89s16r1c40, 40mhz 64kb internal flash mcu general description the sm89s16r1 is a single-chip 8-bits micro- controller manufactured in an advanced cmos process with on chip flash memory. it supports a derivative of the 80c51 microcontroller family. the sm89s16r1 has the same instructions set as the 80c51. the sm89s16r1 contains a 64k x 8 bits on chip program flash, a volatile 1024 x 8 bits data ram, four 8-bits i/o ports, one 4-bits i/o port, two 16-bits timer/event counters, and an additional 16-bits timer coupled to capture and compare latches, a two-priority-level, nested interrupt structure, two pwm clock outputs, one serial interfaces (uart bus). fo r system that requires extra capability the sm89s16r1 can be expanded using standard ttl and lvttl compatible memory and logic. in addition, the sm89s16r1 has two software selectable modes of pow er saving ? idle mode and power-down mode. the idle mode freezes the cpu while allowing the ram, timer, serial ports, and interrupt system to continue functioning. the power-do wn mode saves the ram contents but freezes the oscillator, causing all other chip functions to be inoperative. ordering information sm89s16r1ihhkl yymmv i: process identif ier {l=3.0v~3.6v,c=4.5v~ 5.5v} hh: working clock in mhz {25, 40} k: package type postfix {as below table} yy: year mm: month v: version identifier { , a, b, ...} l:pb free identifier {no text is non-pb free p is pb free} feature z working voltage: 3.3v or 5.0v. z 80c51 central processor unit (cpu). z 64k x 8 bits on chip flash memory. z 1024 x 8 bits ram, expandable externally to 64kb. z two standard 16-bits timers/counters z an additional 16-bits timer/counter coupled to a capture and compare register. z two 8-bits / 5-bits resolution pulse-width-modulation (pwm) outputs z four 8-bits i/o ports.(for pdip package) z four 8-bits i/o ports pl us one 4-bits i/o port. (for plcc or qfp package) z full-duplex uart z 8 interrupt sources with 2 priority levels z extended temperature range (-40 to +85 ) z software enable/disable ale output pulse z wake-up from powe r-down mode by int0/int1, rtci or h/w reset. z rtc (real time clock) function. z four channels 6-bits analog to digital converter (adc). taiwan 6f, no.10-2 li- hsin 1st road , science-based industrial park, hsinchu, taiwan 30078 tel: 886-3-567-1820 886-3-567-1880 fax: 886-3-567-1891 886-3-567-1894
syncmos technologies international, inc. sm89s16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & rtc & adc & pwm & pdwu embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm89s16r1 08/2006 2 pin configuration figure 1 44l pqfp package pwm1/p1.5 p0.4/ad4 p1.6 p0.5/ad5 p1.7 p0.6/ad6 res p0.7/ad7 rxd/p3.0 #ea p4.3 p4.1 txd/p3.1 ale/x32out #int0/p3.2 #psen/x32in #int1/p3.3 p2.7/a15/adc3 t0/p3.4 p2.6/a14/adc2 t1/p3.5 p2.5/a13/adc1 pwm0/p1.4 p3.6/#we p1.3 p3.7/#rd p1.2 xtal2 t2ex/p1.1 xtal1 t2/p1.0 vss p4.2 p4.0 vdd p2.0/a8 ad0/p0.0 p2.1/a9 ad1/p0.1 p2.2/a10 ad2/p0.2 p2.3/a11 ad3/p0.3 p2.4/a12/adc0 36 37 38 30 34 35 31 32 33 39 40 41 42 43 44 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 figure 3 40l pdip package package spec. package pin / pad frequency 44l pqfp figure 1 25 mhz at 3.3v and 40mhz at 5v 44l plcc figure 2 25 mhz at 3.3v and 40mhz at 5v 40l pdip figure 3 25 mhz at 3.3v and 40mhz at 5v figure 2 44l plcc package pwm1/p1.5 p0.4/ad4 p1.6 p0.5/ad5 p1.7 p0.6/ad6 res p0.7/ad7 rxd/p3.0 #ea p4.3 p4.1 txd/p3.1 ale/x32out #int0/p3.2 #psen/x32in #int1/p3.3 p2.7/a15/adc3 t0/p3.4 p2.6/a14/adc2 t1/p3.5 p2.5/a13/adc1 p1.4/pwm0 #we/p3.6 p1.3 #rd/p3.7 p1.2 xtal2 p1.1/t2ex xtal1 p1.0/t2 vss p4.2 p4.0 vdd a8/p2.0 p0.0/ad0 a9/p2.1 p0.1/ad1 a10/p2.2 p0.2/ad2 a11/p2.3 p0.3/ad3 adc0/a12/p2.4 28 18 19 20 21 22 23 24 25 26 27 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 29 30 31 32 33 34 35 36 37 38 39 pwm1/p1.5 pwm0/p1.4 p1.3 p1.2 t2ex/p1.1 vdd p2.0/a8 p2.1/a9 p0.1/ad1 p2.2/a10 p0.2/ad2 p2.3/a11 p0.3/ad3 p2.4/a12/adc0 p1.6 p1.7 res rxd/p3.0 txd/p3.1 #int0/p3.2 #int1/p3.3 t0/p3.4 t1/p3.5 #we/p3.6 #rd/p3.7 xtal2 xtal1 vss p0.4/ad4 p0.5/ad5 p0.6/ad6 p0.7/ad7 ale/x32out #psen/x32in p2.7/a15/adc3 p2.6/a14/adc2 p2.5/a13/adc1 p0.0/ad0 #ea 20 21 t2/p1.0 39 38 37 40 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
syncmos technologies international, inc. sm89s16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & rtc & adc & pwm & pdwu embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm89s16r1 08/2006 3 block diagram uart int-ram 256x8 timer0 timer1 timer2 int cpu flash 64kx8 ext-ram 768x8 rtc pwm adc ibus c51 core wr res t0 t1 (3) (3) int0 int1 (3) (3) p0 p1 p2 p3 port0 port1 port2 port3 port4 parallel i/o ports & ext. bus p4 x32out x32in ( 4 ) ( 4 ) (3) rd (3) psen ale xtal2 xtal1 ea pwm0 pwm1 (1) (1) t2ex t2 (1) (1) rxd txd (3) (3) adc0 adc1 adc2 adc3 notes: (1): alternate function of p1 (2): alternate function of p2 (3): alternate function of p3 (4): alternate function of ale, psen (2) (2) (2) (2) pdwu (3) (3) int0 int1
syncmos technologies international, inc. sm89s16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & rtc & adc & pwm & pdwu embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm89s16r1 08/2006 4 pin description mnemonic pdip 40 pin pqfp 44 pin plcc 44 pin names and functions vdd 40 38 44 power supply: +5v or +3.3v power supply pin during normal operations and power saving modes. p0.0 ? p0.7 39,38,37,36 35,34,33,32 37,36,35,34 33,32,31,30 43,42,41,40 39,38,37,36 port 0 : port 0 is an open-drain, bidirectional i/o port. port 0 pins that have 1s written to them become floating and can be used as high- impedance inputs. port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. in this application, it uses strong internal pu ll-ups when emitting 1s. port pin alternative function p0.0 ad0 p0.1 ad1 p0.2 ad2 p0.3 ad3 p0.4 ad4 p0.5 ad5 p0.6 ad6 p0.7 ad7 p1.0 ? p1.7 1,2,3,4, 5,6,7,8 40,41,42,43, 44,1,2,3 2,3,4,5, 6,7,8,9 port 1 : an 8-bits bidirectional i/o port with internal pull-ups on all pins. port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (see dc electrical characteristics: iil). port pin alternative function p1.0 t2: timer2 clock output p1.1 t2ex: timer2 reload/capture dir. p1.4 pwm0: pwm channel 0 output p1.5 pwm1: pwm channel 1 output rst 9 4 10 reset : a high on this pin for two machine cycles while the oscillator is running, resets the device. an internal resistor to vss permits a power-on reset using only an external capacitor to vcc. p2.0 ? p2.7 21,22,23,24, 25,26,27,28 18,19,20,21 22,23,24,25 24,25,26,27, 28,29,30,31 port 2: port 2 is an 8-bits bidirectional i/o port with internal pull-ups. port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 2 pins that are ex ternally being pulled low will source current because of the internal pull-ups. (see dc electrical characteristics: iil). port 2 emits the high-order address byte during fetches fro m external program memory and during accesses to external data memory that uses 16-bits addresses (movx @dptr). in this appl ication, it uses strong internal pull-ups when emitting 1s. during accesses to external data memory that uses 8-bits addresses (mov @ri), port 2 emits the contents of the p2 special function register. port pin alternative function p2.0 a8 p2.1 a9 p2.2 a10 p2.3 a11 p2.4 a12/adc0 p2.5 a13/adc1 p2.6 a14/adc2 p2.7 a15/adc3 mnemonic pdip 40 pin pqfp 44 pin plcc 44 pin names and functions
syncmos technologies international, inc. sm89s16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & rtc & adc & pwm & pdwu embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm89s16r1 08/2006 5 p3.0 ? p3.7 10,11,12,13 14,15,16,17 5,7,8,9, 10,11,12,13 11, 13,14,15, 16,17,18,19 port 3 : port 3 is an 8-bits bidirectional i/o port with internal pull-ups. port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 3 pins that are ex ternally being pulled low will source current because of the pull-ups. (see dc electrical characteristics: iil). port 3 also serves the special features. port pin alternative function p3.0 rxd uart input p3.1 txd uart output p3.2 #ex0 external interrupt 0 p3.3 #ex1 external interrupt 1 p3.4 t0: timer 0 external input p3.5 t1: timer 1 external input p3.6 #wr external data memory write strobe p3.7 #rd external data memory read strobe ale/x32out 30 27 33 address latch enable : output pulse for latching the low byte of the address during an access to external memory. in normal operation, ale is emitted twice every machine cycle, and can be used for external timing or clocking. note that one ale pulse is skipped during each access to ex ternal data memory. setting sfr sconf.0 can disable ale. with this bits set, ale will be active only during a movx instruction. x32out: the 32.768khz crystal output for rtc function. #psen/x32in 29 26 32 program store enable : the read strobe to external program memory. when executing code from the external program memory, #psen is activated twice each machine cycle, except that two #psen activations are skipped during each access to external data memory. #psen is not activated during fetches from internal program memory. x32in: the 32.768khz crystal input for rtc function. #ea 31 29 35 external access enable: #ea must be externally held low to enable the device to fetch code from external program memory locations. if #ea is held high, the device executes from internal program memory. x1 19 15 21 crystal 1 : input to the inverting oscillat or amplifier and input to the internal clock generator circuits. x2 18 14 20 crystal 2 : output from the inverting oscillator amplifier.
syncmos technologies international, inc. sm89s16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & rtc & adc & pwm & pdwu embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm89s16r1 08/2006 6 sfr mapping the special function regist er of sm89s16r1 fall into the following categories z c51 core register: acc, b, dpl, dph, psw, sp z i/o ports: p0,p1, p2, p3, p4 z timer/counter register: t2con, t2mod, tcon, tmod, th0, th1, th2, tl0, tl1, tl2, rcap2l, rcap2h z uart i/o register: sbuf, scon z power and system control register: pcon, sconf z interrupt system register: ip, ie, ip1, ie1, ifr z pwm output register: pwmc0, pwmc1, pwmd0, pwmd1, p1con z adc register: adcsc, adcd, p2con z rtc register: rtcc, rtcs z led driving capability control: ledp0, ledp1, ledp2, ledp3, ledp4 table 1 sfr map $f8 $ff $f0 b 0000 0000 $f7 $e8 $ef $e0 acc 0000 0000 $e7 $d8 p4 xxxx 1111 $df $d0 psw 0000 0000 pwmc0 0000 0000 pwmc1 0000 0000 $d7 $c8 t2con 0000 0000 t2mod xxxx xx00 rcap2l 0000 0000 rcap2h 0000 0000 tl2 0000 0000 th2 0000 0000 $cf $c0 $c7 $b8 ip 0000 0000 ip1 0000 0000 sconf 0000 0000 $bf $b0 p3 1111 1111 pwmd0 0000 0000 pwmd1 0000 0000 $b7 $a8 ie 0000 0000 ie1 0000 0000 ifr 0000 0000 $af $a0 p2 1111 1111 rtcs 0000 0000 rtcc 0000 0000 $a7 $98 scon 0000 0000 sbuf xxxx xxxx p1con 0000 0000 p2con 0000 0000 $9f $90 p1 1111 1111 ledp0 0000 0000 ledp1 0000 0000 ledp2 0000 0000 ledp3 0000 0000 ledp4 0000 0000 $97 $88 tcon 0000 0000 tmod 0000 0000 tl0 0000 0000 tl1 0000 0000 th0 0000 0000 th1 0000 0000 adcsc 0000 0000 adcd 0000 0000 $8f $80 p0 1111 1111 sp 0000 0111 dpl 0000 0000 dph 0000 0000 pcon 0000 0000 $87 table 2 : all sfr list (8051, i/o, timer, uart, system, interrupt, ram control, pwm, rtc, adc) symbol description direct bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset
syncmos technologies international, inc. sm89s16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & rtc & adc & pwm & pdwu embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm89s16r1 08/2006 7 8051 core acc* accumulator e0 00h b b register f0 00h sp stack pointer 81h 07h psw* process status d0h cy ac f0 rs1 rs0 ov p 00h dptr data pointer (2 bytes) dph data pointer high 82h 00h dpl data pointer low 83h 00h i/o port p0* port 0 80h p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 ffh p1* port 1 90h p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 ffh p2* port 2 a0h p2.7 p2.6 p2.5 p2.4 p2.3 p2.2 p2.1 p2.0 ffh p3* port 3 b0h p3.7 p3.6 p3.5 p3.4 p3.3 p3.2 p3.1 p3.0 ffh p4* port 4 d8h p4 .3 p4.2 p4.1 p4.0 xfh p1con p1 control 9bh pwm1e pwm0e - - 00h p2con p2 control 9ch adc3e adc2e adc1e adc0e - - 00h timer / counter tcon* timer control register 88h tf1 tf1 tf0 tr0 ie1 it1 ie0 it0 00h thl0 timer 0 (2 bytes) th0 timer 0 high 8ch 00h tl0 timer 0 low 8ah 00h thl1 timer 1 (2 bytes) th1 timer 1 high 8dh 00h tl1 timer 1 low 8bh 00h t2con* timer 2 control c8h tf2 exf2 rclk tclk exen2 tr2 ct2 cprl2 00h t2mod timer 2 mode c9h t2oe dcen x0h rcap2hl reload/capture (2 bytes) rcap2h rcap2 high cbh 00h rcap2l rcap2 low cah 00h thl2 time 2 (2 bytes) th2 timer 2 high cdh 00h tl2 time 2 low cch 00h uart scon* uart control 98h sm0 sm1 sm2 ren tb8 rb8 ti ri 00h sbuf uart buffer 99h xxh a/d converter adscr adc status & control 8eh com con adcss1 adcss0 ch1 ch0 00h adcd adc data register 8fh ad. 5 ad.4 ad.3 ad.2 ad.1 ad.0 00h real timer clock (rtc) rtcs rtc status a1h rtcen stable s ec.5 sec.4 sec.3 sec. 2 sec.1 sec.0 00h rtcc rtc control a2h int_sel.1 int_sel.0 min.5 min.4 min.3 min.2 min.1 min.0 00h pwm output pwmc0 pwm 0 control d3h pbs pfs1 pfs0 00h pwmc1 pwm 1 control d4h pbs pfs1 pfs0 00h pwmd0 pwm 0 data b3h pwmd.7 pwmd.6 pwmd.5 pwmd.4 pwmd.3 pwmd.2 pwmd.1 pwmd.0 00h pwmd1 pwm 1 data b4h pwmd.7 pwmd.6 pwmd.5 pwmd.4 pwmd.3 pwmd.2 pwmd.1 pwmd.0 00h power and system pcon power control register 87h smod pd idle 00h sconf system control bfh pdwue ome alei 00h interrupt system ie* interrupt enable a8h ea et2 es0 et1 ex1 et0 ex0 00h ie1 interrupt enable 1 a9h eadc ertc 00h ifr interrupt flag 1 aah adcif rtcif 00h ip* interrupt priority b8h pt2 ps0 pt1 px1 pt0 px0 00h ip1 interrupt priority 1 b9h padc prtc 00h led driving capability control ledp 0 led output in p0 92h 00h ledp 1 led output in p1 93h 00h ledp 2 led output in p2 94h 00h ledp 3 led output in p3 95h 00h ledp 4 led output in p4 96h 00h
syncmos technologies international, inc. sm89s16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & rtc & adc & pwm & pdwu embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm89s16r1 08/2006 8 target spec. absolute rating symbol description min. typ. max. unit. remarks ta operating temperature -40 25 85 ambient temperature under bias vcc5 supply voltage 4.5 5.0 5.5 v vcc3.3 supply voltage 3.0 3.3 3.6 v fosc 25 oscillator frequency 25 mhz for 3.3v application fosc 40 oscillator frequency 40 mhz for 5.0v application dc characteristic vcc = 5v ( 10%), vss=0v ta= -40 to 85 limits symbol parameter test conditions min max unit vcc supply voltage 4.5 5.5 v icc supply current operating see notes 1 f clk = 12mhz vcc = 5.5v 20 ma iid supply current idle mode see note 2 f clk = 12mhz vcc = 5.5v 6.5 ma supply current power-down mode rtc disable see note 3 vcc (= 5.5v) 30 a ipd supply current power-down mode rtc enable see note 3 vcc (= 5.5v) 80 a input vil1 input low voltage, p0, p1, p2, p3, p4, /ea -0.5 0.8 v vil2 input low voltage, res, xtal1 0 0.8 v vih1 input high voltage, p0, p1, p2, p3, p4, /ea 2.0 vcc+0.5 v vih2 input high voltage, res, xtal1 70%vcc vcc+0.5 v iil input current low level port 1,2,3,4 vin = 0.45v -75 a itl transition current high to low port 1,2,3,4 vin = 2.0 v -650 a ili input leakage current ,port 0 0.45v < vin < vcc-0.3v 10 a output vol1 output low voltage , port 0,ale, /psen iol = 8ma vcc=5.0v 0.45 v vol2 output low voltage , port 1, 2, 3, 4 iol = 6.5ma vcc =5.0v 0.45 v voh1 output high voltag e port0 ale, /psen ioh = -800ua vcc =5.0v 2.4 v voh2 output high volt age port 1,2,3,4 ioh = -60 a vcc =5.0v 2.4 v rrst internal reset pull-down resistor 50 300 k ? cio pin capacitance test freq=1mhz, ta=25 10 pf vcc = 3.3v ( 10%), vss=0v , ta= -40 to 85 limits symbol parameter test conditions min max unit vcc supply voltage 3.0 3.6 v icc supply current operating see note 1 f clk = 12mhz vcc = 3.6v 10 ma iid supply current idle mode see note 2 f clk = 12mhz vcc = 3.6v 5 ma supply current power-down mode rtc disable see note 3 vcc (= 3.6v) 20 a ipd supply current power-down mode rtc enable see note 3 vcc (= 3.6v) 30 a input vil1 input low voltage, p0, p1, p2, p3, p4, /ea vcc = 3.6v 0 0.2 vcc -0.2 v vil2 input low voltage, rst vcc = 3.6v 0 0.2 vcc -0.2 v vil3 input low voltage, xtal1 vcc = 3.6v 0 0.2 vcc -0.2 v
syncmos technologies international, inc. sm89s16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & rtc & adc & pwm & pdwu embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm89s16r1 08/2006 9 vih1 input high voltage, p0, p1, p2, p3, p4, /ea vcc = 3.6v 0.6 vcc -0.4 vcc + 0.2 v vih2 input high voltage, rst vcc = 3.6v 0.6 vcc -0.4 vcc + 0.2 v vih3 input high voltage, xtal1 vcc = 3.6v 0.8 vcc vcc + 0.2 v iin1 input current low level port 1,2,3,4 vcc = 3.0v ~3.6v, vin = 0.45v. -10 50 a itl transition current high to low port 1,2,3,4 see note 4 vcc = 3.6v, vin = 2.0 v -75 400 a ili input leakage current p0, /ea vcc = 3.0v ~3.6v, 0.45v 100pf), the noise pulse on the ale pin may exceed 0.8v. in such cases, it may be desirable to qualify ale with a schmitt trigger, or use an address latch with a schmitt trigger strobe input. ac characteristic vcc=3.3v 10%, vss=0v, tclk min = 1/ fm ax(maximum operating frequency)
syncmos technologies international, inc. sm89s16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & rtc & adc & pwm & pdwu embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm89s16r1 08/2006 10 ta= -40 to +85 c l =100pf for port0, ale and /psen; c l =80pf for all other outputs unless otherwise specified. symbol figure parameter min max unit external clock drive into xtal1 tclk 4 xtal1 period 40(1) - ns tclkh 4 xtal1 high time 20 - ns tclkl 4 xtal1 low time 20 - ns tclkr 4 xtal1 rise time - 10 ns tlliv 4 xtal1 fall time - 10 ns tcyc 4 controller cycle time = tclk / 4 3.33 - ns notes: 1. operating at 25mhz. symbol figure parameter min max unit program memory 1/tclk 7 system clock frequency 3.0 25 mhz tlhll 7 ale pulse width 2tclk-40 ns tavll 7 address valid to ale low tclk-40 ns tllax 7 address hold after ale low tclk-30 ns tlliv 7 ale low to valid instruction in 4tclk-100 ns tllpl 7 ale low to /psen low tclk-30 ns tplph 7 /psen pulse width 3tclk-45 ns tpliv 7 /psen low to valid instruction in 3tclk-105 ns tpxix 7 input instruction hold after /psen 0 ns tpxiz 7 input instruction float after /psen tclk -25 ns taviv 7 address to valid instruction in 5tclk-105 ns tplaz 7 /psen low to address float 10 ns data memory tavll 8,9 address valid to ale low tclk-40 ns tllax 8,9 address hold after ale low tclk-35 ns trlrh 8 /rd pulse width 6tclk-100 ns twlwh 9 /wr pulse width 6tclk-100 ns trldv 8 /rd low to valid data in 5tclk-165 ns trhdx 8 data hold after /rd 0 ns trhdz 8 data float after /rd 2tclk-70 ns tlldv 8 ale low to valid data in 8tclk-150 ns tavdv 8 address to valid data in 9tclk-165 ns tllwl 8,9 ale low to /rd or /wr low 3tclk-50 3tclk+50 ns tavwl 8,9 address valid to /wr or /rd low 4tclk-130 ns tqvwx 9 data valid to /wr transition tclk-50 ns tqvwh 9 data before /wr 7tclk-150 ns twhqx 9 data hold after /wr tclk-50 ns trlaz 8 /rd low to address float 0 ns twhlh 8,9 /rd or /wr high to ale high tclk-40 tclk+40 ns uart txlxl 10 serial port clock time 12tclk ns tqvxh 10 output data setup to cl ock rising edge 10tclk-133 ns txhqx 10 output data hold after cloc k rising edge 2tclk-117 ns txhdx 10 input data hold after clock rising edge 0 ns txhdv 10 clock rising edge to input data valid 10tclk-133 ns
syncmos technologies international, inc. sm89s16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & rtc & adc & pwm & pdwu embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm89s16r1 08/2006 11 figure 4 external clock drive waveform figure 5 ac testing input/output figure 6 ac testing, floating waveform ale /psen port0 port2 a0-a7 instr in a0-a7 a8-a15 a8-a15 a8-a15 a8-a15 t lhll t llpl t plph t llax t aviv t avll t lliv t plaz t pxix t pxiz t pliv figure 7 external program memory read cycle floating 2.0v 0.8v 0.8v 2.0v notes: the float state is define as the point which port 0 pins sinks 3.2ma or source 400 a at the voltage test level. test points 2.0v 0.8v 0.8v 2.0v notes: ac inputs during testing are driven at 2.4v for logic ?high? and 0.45v for logic ?low?. timing measurements are at 2.0v for logic ?high? and 0.8v t clkh t clkl 0.8v t cl k v ih1 t clkr t lliv
syncmos technologies international, inc. sm89s16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & rtc & adc & pwm & pdwu embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm89s16r1 08/2006 12 ale /psen /rd port0 port2 a0 - a7 (ri or dpl) data in a0 - a7 (pcl) instr in a8 - a15 of dph or port2 a8 - a15 (pch) t avwl t avdv t rlaz t rldv t rlrh t lldv t whlh t rhdz t rhdx t avll t llax t llwl figure 8 external data memory read cycle ale /psen /wr port0 port2 a0 - a7 (ri or dpl) data out a0 - a7 (pcl) instr in a8 - a15 of dph or port2 a8 - a15 (pch) t avwl t wlwh t whqx t avll t llax t llwl t whlh t qvwx t qvwh figure 9 external data memory write cycle i nstruction ale clock txd rxd 0 0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 valid valid valid valid valid valid valid valid set_ri t xlxl t qvxh t xhqx t xhdv t xhdx figure10 uart waveform in shift register mode
syncmos technologies international, inc. sm89s16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & rtc & adc & pwm & pdwu embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm89s16r1 08/2006 13 function description the sm89s16r1 is a stand-alone high-performance microcont roller designed for use in many applications, such as lcd monitor, instrumentation, or high-end consumer applications. in addition to the 80c51 standard func tions, the device provides a number of dedicated hardware functions for these applications. the sm89s16r1 is a control-oriented cpu with on-chip progr am and data memory. it can be extended with external data memory up to 64k bytes. for system requiring ex tra capability, the sm89s16r1 can be enhanced by using external memory and peripherals. the sm89s16r1 has two software selectab le modes of saving power consumption idle and power-down. the idle mode freezes the cpu while allowing the ram, timer, seria l ports and interrupt system to continue functioning. the power-down mode save the ram contents but freezes th e oscillator causing all other chip functions to be inoperative. the power-down mode can be terminated by h/ w reset, or by any one of the two external interrupt or rtci function. cpu the cpu of sm89s16r1 is compatible to standard 80c51. the structure of this cpu is shown as figure 11. it contains instruction register (ir), instruction decoder, and program counter (pc), accumulator (acc), b register, and control logic. this cpu provides a 8-bits bi-directi on bus to communicate with other blocks in the chip. the address and data are transferred through on the same 8-bits bus. figure 11 the cpu structure cpu timing the machine cycle consists of a sequence of 6 states, numbere d s1 through s6. each state time lasts for two oscillator periods. thus a machine cycle takes 12 oscillator periods. e ach state is divided into a phase 1 half and a phase2 half. figure 12 shows relationships betw een oscillator, phase, and s1-s6. alu ir q res cl k data in/out ctrl. bus prog. addr. power ctrl.signal control logic timing & reset instruction decoder instruction register sp b re g iste r psw acc tmp1 tmp2 program addr.register buffer program increment program counter dptr pcon
syncmos technologies international, inc. sm89s16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & rtc & adc & pwm & pdwu embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm89s16r1 08/2006 14 figure 12 sequences and phases figure 12 shows the fetch / execute sequences in states and phases for various kinds of instructions. normally the program fetches are generated during each machine cycle, ev en if the instruction being executed doesn?t require it. if the instruction being executed doesn?t need more code bytes, the cpu simply ignores the extra fetch, and the program counter is incremented accordingly. execution of a one-cycle instruction (figure 13a and b) begins during s1 of the machine cycle, when the opcode is latched into instruction register. a second fe tch occurs during s4 of the same machine cycle. execution is completed at the end of s6 of this machine cycle. the movx instructions take two machine cycles to execute . no program fetch is generated during the second cycle of a movx instruction. this is the only time program fe tches are skipped. the fetch/execute sequence for movx instructions is shown in figure13 (d) the fetch/execute sequences are the same whether the pr ogram memory is internal or external to the chip. execution times do not depend on whether the pr ogram memory is internal or external. figure 14 shows the signals and timing involved in progr am fetches when the program memory is external. if program memory is external, the program memory read stobe (/psen) is normally activated twice per machine cycle, as shown in figure 14(a). if an access external data memory occurs, as shown in figure 14(b), two (/psen) are skipped, because the address and data bus are being used for data memory access. note that a data memory bus cycle takes twice as much time as program memory bus cycle. figure 14 shows the relative time of the address begin emitted at po rt0 and port2, and of ale and /psen. ale is used to latch the low address byte form port0 into the address latch. when cpu is executing from internal program memory, /psen is not activated, and program address is not emitted. however, ale continues to be activated twice per machine cycle and so is available as clock output signal. note, however, that ale is skipped duri ng the execution of the movx instruction. p1 p2 p1 p2 p1 p2 p1 osc (xtal2) p2 p1 p2 p1 p2 p1 p2 p1 s1 s2 s3 s4 s5 s6 s1 s2 phase sequence
syncmos technologies international, inc. sm89s16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & rtc & adc & pwm & pdwu embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm89s16r1 08/2006 15 figure 13 timing of various instructions a.) 1 byte, 1 cycle instruction read opcode read next opcode discard read next opcode again 1 machine cycle s1 s2 s3 s4 s5 s6 s1 s2 b.) 2 byte, 1 cycle instruction read opcode read 2?nd byte read next opcode 1?st cycle c.) 1 byte, 2 cycle instruction read opcode read next opcode again 1 machine cycle 2?nd cycle read next opcode (discard) 1?st cycle d.) movx: 1 byte, 2 cycle instruction read opcode read next opcode again 2?nd cycle read next opcode (discard) no fetch no fetch access external memory addr data s1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 s1 s2 s1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 s1 s2 s1 s2 s3 s4 s5 s6 s1 s2
syncmos technologies international, inc. sm89s16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & rtc & adc & pwm & pdwu embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm89s16r1 08/2006 16 figure 14: bus cycle in exte rnal program memory mode instruction set the sm89s16r1 uses the powerful instruction set of 80c51. it consists of 49 single-byte, 42 two-byte, and 15 three- byte instructions. among them 63 instruction are executed in 1 machine-cycle, 46 instructions in 2 machine-cycles, and the multiply, 2 instructions in 4 machine-cycles. a summary of the instruction set is given in table 3. one cycle a.) without movx s1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 s1 s2 one cycle ale /psen /rd p2 pch out pch out pch out pch out pcl out inst. in pcl out inst. in pcl out inst. in pcl out inst. in pcl out p0 1?st cycle a.) with movx 2?nd cycle ale /psen /rd p2 pch out p2 or dph out pch out pcl out inst. in addr. out data. in pcl out inst. in pcl out p0 s1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 s1 s2
syncmos technologies international, inc. sm89s16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & rtc & adc & pwm & pdwu embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm89s16r1 08/2006 17 addressing mode notes on instruction set and address modes: rn register r7-r0 of the curre ntly selected register bank. direct 8-bits internal data location?s address. th is could be internal data ram location (0-127) or a sfr [i.e., i/o port, control register, status register, etc. (128-255)] @ri 8-bits ram location addressed indirectly through register r1 or r0 of the actual register bank #data 8-bits constant included in the instruction #data16 16-bits constant included in the instruction addr11 11-bits destination address. used by acal l and ajmp. the branch can be anywhere within the same 2 kbytes page of program memory as the first byte of the following instruction. rel signed (2?s complement) 8-bits offset byte. used by sjmp and all conditional jumps. range is -128 to +127 bytes relative to first byte of the following instruction. bit direct addressed bit in internal data ram or sfr table 3: a summary of the instruction set mnemonic operation byte cycle arithmetic instructions add a,rn a = a + rn 1 1 add a,direct a = a + direct 2 1 add a,@ri a = a + <@ri> 1 1 add a,#data a = a + #data 2 1 addc a,rn a = a + rn + c 1 1 addc a,direct a = a + direct + c 2 1 addc a,@ri a = a + @ri + c 1 1 addc a,#data a = a + #data + c 2 1 subb a,rn a = a rn c 1 1 subb a,direct a = a direct c 2 1 subb a,@ri a = a <@ri> c 1 1 subb a,#data a = a #data c 2 1 inc a a = a + 1 1 1 inc rn rn = rn + 1 1 1 inc direct direct = direct + 1 2 1 inc @ri <@ri> = <@ri> + 1 1 1 dec a a = a 1 1 1 dec rn rn = rn 1 1 1 dec direct direct = direct 1 2 1 dec @ri <@ri> = <@ri> 1 1 1 inc dptr dptr = dptr 1 1 2 mul ab b:a = a b 1 4 div ab a = int (a/b) b = mod (a/b) 1 4 da a decimal adjust acc 1 1 logical instructions anl a,rn a .and. rn 1 1 anl a,direct a .and. direct 2 1 anl a,@ri a .and. <@ri> 1 1 anl a,#data a .and. #data 2 1 anl direct,a direct .and. a 2 1 anl direct,#data direct .and. #data 3 2 orl a,rn a .or. rn 1 1 orl a,direct a .or. direct 2 1 orl a,@ri a .or. <@ri> 1 1 orl a,#data a .or. #data 2 1 orl direct,a direct .or. a 2 1 orl direct,#data direct .or. #data 3 2 xrl a,rn a .xor. rn 1 1 xrl a,direct a .xor. direct 2 1 xrl a,@ri a .xor. <@ri> 1 1 xrl a,#data a .xor. #data 2 1 xrl direct,a direct .xor. a 2 1 xrl direct,#data direct .xor. #data 3 2 clr a a = 0 1 1 cpl a a = /a 1 1 rl a rotate acc left 1 bit 1 1
syncmos technologies international, inc. sm89s16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & rtc & adc & pwm & pdwu embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm89s16r1 08/2006 18 rlc a rotate left through carry 1 1 rr a rotate acc right 1 bit 1 1 rrc a rotate right through carry 1 1 swap a swap nibbles in a 1 1 data transfers instructions mov a,rn a = rn 1 1 mov a,direct a = direct 2 1 mov a,@ri a = <@ri> 1 1 mov a,#data a = #data 2 1 mov rn,a rn = a 1 1 mov rn,direct rn = direct 2 2 mov rn,#data rn = #data 2 1 mov direct,a direct = a 2 1 mov direct,rn direct = rn 2 2 mov direct,direct direct = direct 3 2 mov direct,@ri direct = <@ri> 2 2 mov direct,#data direct = #data 2 1 mov @ri,a <@ri> = a 1 1 mov @ri,direct <@ri> = direct 2 2 mov @ri,#data <@ri> = #data 2 1 mov dptr,#data16 dptr = #data16 3 2 movc a,@a+dptr a = code memory[a+dptr] 1 2 movc a,@a+pc a = code memory[a+pc] 1 2 movx a,@ri a = external memory [ri] (8-bits address) 1 2 movx a,@dptr a = external memory [dptr] (16-bits address) 1 2 movx @ri,a external memory[ri] = a (8-bits address) 1 2 movx @dptr,a external memory[dpt r] = a (16-bits address) 1 2 push direct inc sp: mov ?@?sp?, < direct > 2 2 pop direct mov < direct >, ?@sp?: dec sp 2 2 xch a,rn acc and < rn > exchange data 1 1 xch a,direct acc and < direct > exchange data 2 1 xch a,@ri acc and < ri > exchange data 1 1 xchd a,@ri acc and @ri exchange low nibbles 1 1 boolean instructions clr c c = 0 1 1 clr bit bit = 0 2 1 setb c c = 1 1 1 setb bit bit = 1 2 1 cpl c c = /c 1 1 cpl bit bit = /bit 2 1 anl c,bit c = c .and. bit 2 2 anl c,/bit c = c .and. /bit 2 2 orl c,bit c = c .or. bit 2 2 orl c,/bit c = c .or. /bit 2 2 mov c,bit c = bit 2 1 mov bit,c bit = c 2 2 jc rel jump if c= 1 2 2 jnc rel jump if c= 0 2 2 jb bit,rel jump if bit = 1 3 2 jnb bit,rel jump if bit = 0 3 2 jbc bit,rel jump if c = 1 3 2 jump instructions acall addr11 call subroutine only at 2k bytes address 2 2 lcall addr16 call subroutine in max 64k bytes address 3 2 ret return from subroutine 1 2 reti return from interrupt 1 2 ajmp addr11 jump only at 2k bytes address 2 2 ljmp addr16 jump to max 64k bytes address 3 2 sjmp rel jump on at 256 bytes 2 2 jmp @a+dptr jump to a+ dptr 1 2 jz rel jump if a = 0 2 2 jnz rel jump if a 0 2 2 cjne a, direct,rel jump if a < direct > 3 2 cjnz a, #data,rel jump if a < #data > 3 2 cjnz rn, #data,rel jump if rn < #data > 3 2 cjnz @ri, #data,rel jump if @ri < #data > 3 2 djnz rn,rel decrement and jump if rn not zero 2 2
syncmos technologies international, inc. sm89s16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & rtc & adc & pwm & pdwu embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm89s16r1 08/2006 19 djnz direct,rel decrement and jump if direct not zero 3 2 nop no operation 1 1 memory organization the central processing unit (cpu) manipulates operands in thr ee memory spaces; there are 1024 bytes internal data memory (consisting of 256 bytes standard ram and 768 by tes aux-ram) and 64k bytes internal/external program memory (see figure 15) figure 15 memory organization of sm89s16r1 program memory the program memory of sm89s16r1 consists of 64k byt es flash memory on chip. if during reset, the /ea pin was held high, the sm89s16r1 does not execute out of th e internal program memory. if the /ea pin was held low during reset the sm89s16r1 fetch all instruc tions from the external program memory. external writer can program it. the feature of flash memory is shown as following z read: byte-wise z write: byte-wise within 30us (previously erased by a chip erase). z erase: page erase (512 bytes) within 10 ms full erase (64k bytes) within 2 sec. erased bytes contain ffh z endurance : 10k erase and write cycles each byte at ta=25 z retention : 10 years internal flash memory /ea=1 0000 64k external flash memory /ea=0 program memory indirect only direct and indirect 0000 0080 02ff overlapped space direct (sfr) xram (ome=1) xram ome=0 0000 64k internal data memory external data memory
syncmos technologies international, inc. sm89s16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & rtc & adc & pwm & pdwu embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm89s16r1 08/2006 20 internal data memory the data memory of sm89s16r1 consists of 1024 bytes internal data memory (256 bytes standard ram and 768 bytes aux-ram). the aux-ram is enable by sconf.1 ($bf.1), and read/write by movx analog to digital converter (adc) the adc block diagram was shown as below: those are only 4 pins mirror to port 2[7:4] at vin<3:0>. the digital output data [11:4] were put into adcd ($8fh). and the adc interrupt vector is 4bh. the adc sfr shown as below: adscr ($8eh) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 com con adcss1 adcss0 ch1 ch0 com: read only. when convers ion complete, it will be set. con: when set, the adc will conversion c ontinuous, else it will conversion only once. adcss [1:0]: adc clock select. (adc_clk range 500 khz~2.5 mhz).if over frequency of adc_clk, the conversion data may be unstable. adcss1 adcss0 adc_clk 0 0 fosc/8 0 1 fosc/16 1 0 fosc/32 1 1 fosc/64 ch [1:0]: adc channel select. ch1 ch0 input select 0 0 ch0 0 1 ch1 1 0 ch2 1 1 ch3 adcd ($8fh) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ad.5 ad.4 ad.3 ad.2 ad.1 ad.0 *read only. 6-bit sar adc vss vdd(=vref) adc_clk 4 vain<3:0>{p2.4~p2.7} ch<2:0>{adscr[3:2]} 3 6 data<5:0> {adcd[7:2]} adcss1 adcss0 adc_clk 0 0 fosc/4 0 1 fosc/8 1 0 fosc/16 1 1 fosc/32 adcss[1:0]= {adscr[5:4]} continuous{adscr.6} complete {adscr.7} figure 16 adc block diagram
syncmos technologies international, inc. sm89s16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & rtc & adc & pwm & pdwu embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm89s16r1 08/2006 21 pulse width modulation (pwm) the pwm output pins are p1.4 and p1.5. the pwm clock is {fosc/ (2xdivider)}, the pwm output frequency is {(pwm clock)/32} at 5 bits resolution and {(pwm clock)/256} at 8 bits resolution. the pwm sfr show as below: pwmc ($d3h and $d4h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 pbs pfs1 pfs0 pbs: when set, the pwm is 5 bits resolution. pfs [1:0]: the pwm clock divider select. pfs1 pfs0 pwm clock divider select 0 0 2 0 1 4 1 0 8 1 1 16 pwmd ($b3h and $b4h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 pwmd.7 pwmd.6 pwmd.5 pwmd.4 pwmd.3 pwmd.2 pwmd.1 pwmd.0 real time clock (rtc) the on-chip rtc keeps time of second and minute functions. its time base is a 32.768 khz crystal between pins x32out (alternate function of ale) and x32in (alternate function of psen). the rtc maintains time to a second. it also allows a user to read (and write) seconds and minute. the rtc function used sfr descriptor as below: rtcs ($a1h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rtcen stable sec.5 sec.4 sec.3 sec.2 sec.1 sec.0 rtcen: when set to ?1?, enable the enable rtc functi on. when this bit set, the ale and psen pins output will disable, and the ale and psen pins will u se for rtc function as x32out and x32in. stable: read only. the stable bit will set to 1 when the rtc module stable. please wait 2 seconds before used the rtc function. sec [5:0]: show the current second counter at rtc function. the range is from 00h to 3bh. rtcc ($a2h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 int_sel1 int_sel0 min.5 min.4 min.3 min.2 min.1 min.0 int_sel [1:0]: the interrupt distribution selection bit, the interrupt vector is 43h. 00: the interrupt is set as 0.5 second 01: the interrupt is set as 1 second 10: the interrupt is set as 30 second 11: the interrupt is set as 60 second min [5:0]: show the current minute counter at rtc function. the range is from 00h to 3bh.
syncmos technologies international, inc. sm89s16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & rtc & adc & pwm & pdwu embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm89s16r1 08/2006 22 starting and stopping the rtc: rtcs ($a1h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rtcen stable sec.5 sec.4 sec.3 sec.2 sec.1 sec.0 the rtc function is enable by set the rtcs.7 (rtcen=1), then the ale and /psen pins will switch to x32out and x32in that for rtc function used, the ale and psen signal output will disable; the crystal frequency is 32.768 khz. see figure 17. 1 2 j1 x32in ( /psen ) 1 r j2 x32out ( ale ) 1 rtcen sw 1 1 2 32768hz clock in y1 32768hz in c hip figure 17 the rtc crystal connect diagram the stable bit (rtcs.6) will set to 1 when the rtc modul e stable. the design is about 31.25 ms; suggest waiting 2 second to use the rtc function. this bit will clear when rtcen bit set again. the sec [5:0] will show the second counter (range from 00h to 3bh), and the min [5:0] will show the minute counter (range from 00h to 3bh) of rtc function. this two register will clear when rtcen bit set. interrupt: ie1 ($a9h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 eadc ertc ertc: when set to ?1?, enable the rtc interrupt. if you want to use the rtc interrupt function, must enable the ea bit in ie.7 and enable the ertc bit in ie1.2. eadc: when set to ?1?, enable the adc interrupt. if you want to use the adc interrupt function, must enable the ea bit in ie.7 and enable the eadc bit in ie1.3 rtcc ($a2h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 int_sel1 int_sel0 min.5 min.4 min.3 min.2 min.1 min.0 then select the interrupt distributi on in int_sel [1:0] in rtcc [7:6]. the rtc can select each of 4 interrupt sources: 0.5 second, 1 second, 0.5 minute, and 1 minute. the interrupt vector is 43h, it can wake-up cpu from power-down mode. ifr ($aah) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 adcif rtcif adcif: when interrupt occupy the adc interrupt flag (if r.3) will set, and the cpu will execute the interrupt subroutine at the interrupt vector 4bh. the adc interrupt flag must clear by software. rtcif: when interrupt occupy the rtc interrupt flag (ifr.2) will set, and the cpu will execute the interrupt subroutine at the interrupt vector 43h. the rt c interrupt flag must clear by software.
syncmos technologies international, inc. sm89s16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & rtc & adc & pwm & pdwu embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm89s16r1 08/2006 23 ip1 ($b9h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 padc prtc the interrupt priority can be set at ip1.2 or ip1.3. padc: when set to ?1?, enable the adc interrupt priority. prtc: when set to ?1?, enable the rtc interrupt priority. divider 2 int 1min sec4 min0 divider 2 int 1sec sec0 min4 sec5 5 bits shif register int out rtcen u2 74151 4 3 2 1 15 14 13 12 11 10 9 7 6 5 d0 d1 d2 d3 d4 d5 d6 d7 a b c g y y min1 sec1 divider 30 min5 second register int 0.5min sec2 32768hz clock in min2 int sel0 divider 16384 minute register 5 bits shif register sec3 int 0.5sec min3 int sel1 figure 18 the rtc block diagram led driving capability control this function is set the sink current more then 10 ma for each pin, 26 ma for whole port 0, 15 ma for whole port 1 or whole port2 or whole port3 or whole port4, and total 71 ma for whole chip. the sfr show as below: port name sfr address iol(max) for total port port0 $92h 26 ma port1 $93h 15 ma port2 $94h 15 ma port3 $95h 15 ma port4 $96h 15 ma the power down wake up (pdwu) function the device can be put into power down mode by writing 1 to bit pcon.1. the instruction that does this will be the last instruction to be executed before the device goes in to power down mode. in the power down mode, all the clocks are stopped and the device comes to a halt. all activ ity is completely stopped and the power consumption is reduced to the lowest possible value. in this state the ale and psen pins are pulled low. the port pins output the values held by their respective sfrs.
syncmos technologies international, inc. sm89s16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & rtc & adc & pwm & pdwu embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm89s16r1 08/2006 24 the sm89s16r1 will exit the power down mode with a reset or by a rtc (real time clock) interrupt or by an external interrupts pin enabled as level detects. 1. an external reset can be used to exit the power down state. the high on rs t pin terminates the power down mode, and restarts the clock. the program execution will restart from 0000h. 2. an external interrupt pin and rtc interrupt can be used to exit the power down state wh en the external interrupt or rtc interrupt actives and provided the corresponding interrupt is enabled, while the global enable (ea) bit is set and the external input has been set to a level detect mode or rtc interrupt set. if these conditions are met, then the low level on the external pin or rtc interrupt re-starts the osc illator. then device executes th e interrupt service routine for the corresponding external interrupt or rtc interrupt. after the interrupt service routine is completed, the program execution returns to the instruction after the one that put the device into power down mode and continues from there. pcon ($87h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 smod pd idle smod: this bit set to ?1? to make the uart baud-rate double. pd: when set to ?1? , the mcu will into power down mode idle: when set to ?1? , the mcu will into idle mode sconf ($bfh) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 pdwue ome alei pdwue: when set to ?1?, enable the pdwu function. ome: when set to ?1?, enable the 768 bytes expanded ram. alei: when set to ?1?, it will stop ale clock output for emi reduce. ie ($a8h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ea et2 es0 et1 ex1 et0 ex0 ea: when set to ?1?, enable interrupt global. et2: when set to ?1?, enable timer2 interrupt. es0: when set to ?1?, enable uart interrupt. et1: when set to ?1?, enable timer1 interrupt. ex1: when set to ?1?, enable external interrupt 1. et0: when set to ?1?, enable timer0 interrupt. ex0: when set to ?1?, enable external interrupt 0. tcon ($88h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 tf1: timer 1 overflow flag. tr1: timer 1 run control bit. tf0: timer 0 overflow flag. tr0: timer 0 run control bit. ie1: external interrupt 1 edge flag. it1: interrupt 1 type control bit. ie0: external interrupt 0 edge flag. it0: interrupt 0 type control bit.
syncmos technologies international, inc. sm89s16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & rtc & adc & pwm & pdwu embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm89s16r1 08/2006 25 ip ($b8h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 pt2 ps0 pt1 px1 pt0 px0 pt2: timer2 interrupt priority. ps0: uart interrupts priority. pt1: timer1 interrupt priority. px1: external interrupt 1 priority. pt0: timer0 interrupt priority. px0: external interrupt 0 priority. the priority structure and v ector locations of interrupts: source flag priority level vector address external interrupt 0 ie0 1(highest) 03h timer 0 overflow tf0 2 0bh external interrupt 1 ie1 3 13h timer 1 overflow tf1 4 1bh uart 0 interrupt ri+ti 5 23h timer 2 overflow tf2+exf2 6 2bh rtc interrupt rtcif 7 43h adc interrupt adcif 8 4bh t2mod ($c9h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 t2oe dcen t2cr: timer 2 capture reset. in the timer2 capture mode this bit enables/disables hardware automatically reset timer2 while the value in tl2 and th2 have been transferred into the capture register. t2oe: timer2 clock output enable bit. if set to 1, the timer2 clock will output to p1.0. dcen: down count enable. when set this bit then allo ws timer2 to be configured as an up/down counter. application reference xi x2 sm89s16r1 x'tal r c1 c2 note: oscillation circuit may differs with differ ent crystal or ceramic resonator in highe r oscillation frequency which was due to ea ch crystal or ceramic resonator has its own characteristics. user should check with the crystal or ceramic resonator manufacturer for appropriate value of external components. valid for sm89s16r1 x'tal 3mhz 6mhz 9mhz 12mhz c1 30 pf 30 pf 30 pf 22 pf c2 30 pf 30 pf 30 pf 22 pf r open open open open x'tal 16mhz 25mhz 33mhz 40mhz c1 30 pf 15 pf 5 pf 2 pf c2 30 pf 15 pf 5 pf 2 pf r open open 6.8k 4.7k
syncmos technologies international, inc. sm89s16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & rtc & adc & pwm & pdwu embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm89s16r1 08/2006 26 pdip 40l (600mil) package informatio n note: 1. refer to jedec std.ms-011(ac). 2. dimension d and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. d and e1 are maximum plastic body size dimension include mold mismatch. 3. dimension b3 does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed the maximum b3 dimension by more than 0.2mm . dimension in mm dimension in mil symbol min nom max min nom max a1 0.254 10 a2 3.683 3.810 3.937 145 150 155 b 0.356 0.500 0.660 14 20 26 b1 0.356 0.457 0.508 14 18 22 b2 1.016 1.270 1.524 40 50 60 b3 1.016 1.321 1.626 40 52 64 c 0.203 0.254 0.432 8 10 17 c1 0.203 0.254 0.356 8 10 14 d 52.07 52.2 52.32 2050 2055 2060 e 14.99 15.24 15.49 590 600 610 e1 13.69 13.87 13.94 539 546 549 e 2.540 100 eb 15.75 16.26 16.76 620 640 660 l 2.921 3.302 3.683 115 130 145 s 1.727 1.981 2.235 68 78 88 q1 1.651 1.778 1.905 65 70 75 0 10 0 10
syncmos technologies international, inc. sm89s16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & rtc & adc & pwm & pdwu embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm89s16r1 08/2006 27 plcc 44l package informatio n unit symbol inch(ref) mm(base) a 0.180(max) 4.572(max) a1 0.024 0.005 0.52 0.14 a2 0.105 0.005 2.667 0.127 b 0.018 + 0.004 - 0.002 0.457 + 0.102 - 0.051 b1 0.028 + 0.004 - 0.002 0.711 + 0.102 - 0.051 c 0.010(typ) 0.254(typ) d 0.690 0.010 17.526 0.254 d1 0.653 0.003 16.586 0.076 d2 0.610 0.020 15.494 0.508 e 0.690 0.010 17.526 0.254 e1 0.653 0.003 16.586 0.076 e2 0.610 0.010 15.494 0.254 e 0.050(typ) 1.270(typ) y 0.003(max) 0.076(max) 0~5 0~5
syncmos technologies international, inc. sm89s16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & rtc & adc & pwm & pdwu embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm89s16r1 08/2006 28 qfp 44l(10x10x2.0mm) package information note: 1. refer to jedc std.ms-022(ab). 2. dimension e1 do not include mold protrusion. allowable protrusion is 0.25mm per side.e1 are maximum plastic body size dimension include mold mismatch . 3. dimension b does not include dambar protrusion .allowable dambar protrusion shall not cause the lead width to exceed the maximum b3 dimension by more than 0.1 mm. dimension in mm dimension in mil symbol min nom max min nom max a 2.45 964 a1 0.05 0.15 0.25 2.1 6.0 9.6 a2 1.90 2.00 2.10 74.8 78.7 82.7 b 0.29 0.32 0.45 11.4 12.6 17.7 b1 0.29 0.30 0.41 11.4 11.8 16.1 c 0.11 0.17 0.23 4.3 6.7 9.1 c1 0.11 0.15 0.19 4.3 5.9 7.5 e 13.00 13.20 13.40 512 520 528 e1 9.90 10.00 10.10 390 394 398 e 0.800 31.5 l 0.73 0.88 1.03 28.7 34.6 40.6 l1 1.50 1.60 1.70 59.1 63.0 66.9 y 0.076 3 0 7 0 7
syncmos technologies international, inc. sm89s16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & rtc & adc & pwm & pdwu embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm89s16r1 08/2006 29 e mcu writer list company contact info programmer model number advantech 7f, no.98, ming-chung rd., shin-tien city, taipei, taiwan, roc web site: http://www.aec.com.tw tel:02-22182325 fax:02-22182435 e-mail: aecwebmaster@advantech.com.tw lab tool - 48xp (1 * 1) lab tool - 848 (1*8) hi-lo 4f, no. 20, 22, ln, 76, rui guang rd., nei hu, taipei, taiwan, roc. web site: http://www.hilosystems.com.tw tel:02-87923301 fax:02-87923285 e-mail: support@hilosystems.com.tw all - 11 (1*1) gang - 08 (1*8) leap 6th f1-4, lane 609, chunghsin rd., sec. 5, sanchung, taipei hsien, taiwan, roc web site: http://www.leap.com.tw tel:02-29991860 fax:02-29990015 e-mail: service@leap.com.tw leap-48 (1*1) su - 2000 (1*8) xeltek electronic co., ltd 338 hongwu road, nanjing, china 210002 web site: http://www.xeltek-cn.com tel:+86-25-84408399, 84543153-206 e-mail: xelclw@jlonline.com, xelgbw@jlonline.com superpro/2000 (1*1) superpro/280u (1*1) superpro/l+(1*1)

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